module romfi (MODE, ADDR, DATA);

input [1:0] MODE;
input [2:0] ADDR;
output [2:0] DATA;

wire [1:0] MODE;
wire [2:0] ADDR;
reg [2:0] DATA;

always @(MODE or ADDR)
begin
	case (MODE)
	2'b11:
		case (ADDR)
		3'b000: DATA = 3'b001;
		3'b001: DATA = 3'b010;
		3'b010: DATA = 3'b011;
		3'b011: DATA = 3'b100;
		3'b100: DATA = 3'b100;
		3'b101: DATA = 3'b101;
		3'b110: DATA = 3'b110;
		3'b111: DATA = 3'b111;
		endcase
	2'b00:
		case (ADDR)
		3'b000: DATA = 3'b001;
		3'b001: DATA = 3'b010;
		3'b010: DATA = 3'b011;
		3'b011: DATA = 3'b100;
		3'b100: DATA = 3'b101;
		3'b101: DATA = 3'b110;
		3'b110: DATA = 3'b111;
		3'b111: DATA = 3'b111; /*Sign-Shift 8 bits === Sign-Shift 7 bits for 8 bits shifter*/
		endcase
	2'b01:
		case (ADDR)
		3'b000: DATA = 3'b000;
		3'b001: DATA = 3'b001;
		3'b010: DATA = 3'b010;
		3'b011: DATA = 3'b011;
		3'b100: DATA = 3'b100;
		3'b101: DATA = 3'b101;
		3'b110: DATA = 3'b110;
		3'b111: DATA = 3'b111;
		endcase
	default:
		DATA = 3'bXXX;
	endcase
end

endmodule
